Hi Cortex-M architects or experts,
I have a question. Is the interrupt vector calculated by not ADDed with VTOR but ORed with VTOR? There is a post in the Freescale Kinetis Community as "Vector Table Offset - is this expected behaviour??" (https://community.freescale.com/thread/337498). His post shows it is ORed. This would be uncertain even if I read ARMv7M Reference Manual. I would like to clarify the fact.
Best regards,Yasuhiko Koumoto.
Hi yasuhikokoumoto san,
Disclaimer first: I am not Cortex-M architect, neither an expert though though your question is addressed to one.
I don't think there is ORing here. Basically the VTOR contains offset to the start of the vector table. By default the VTOR is 0 and therefore the vector table is located at 0x0000 0000. Starting address being the initial stack pointer value.
Any interrupt/exception vector would be calculated by adding the exception number to the offset and reading the contents of this memory location.
The alignment restriction makes the VTOR being written a value of next highest power of 2 from the max number of entries in the table.
Not sure if this helps you.
Thanks,
Gopal
Hi Gopal,
I prefer to your guess but the fact is different. The original post says as the following.In case of VTOR=0x00000000, USB OTG interrupt offset is 0x164 and UART0 interrupt offset is 0x0f4. And if VTOR is set to 0x8080, USB OTC interrupt address became 0x81e4 and UART0 interrupt address is 0x80f4, the former was 0x81e4 (as expected) and the latter was NOT 0x8174 (as not expected).Also my experiment shows the interrupt of 0xf0 offset still invoked from 0xf0 address even if VTOR was set to 0x0080.It shows the interrupt vector offset is calculated by OR-ing.