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Setting up NVIC with ISR in CortexM4

DFinn

Could you please send me a snippet of code to set up the NVIC to use an ISR &  trigger the ISR ?

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  • 0 in reply to DFinn

    Chapter 7 has an example of setting up interrupts right in the chapter as well as an English description of what it is doing.  (Page 268 of the 3rd edition has a "simple" setting up of an interrupt example. )

    It goes like this 

    // No need to set priority grouping just yet, use the default

    // No need to set the priority just yet, use the default

    NVIC_EnableIRQ(IRQn);

    If you want to execute this interrupt through software

    NVIC_SetPendingIRQ(IRQn);

    Normally the hardware would assert the interrupt pending and not the software, but this would let you test the IRQ out.

    When the Interrupt happens the processor will enter the Exception sequence ending with loading the PC with the address in the Vector Table at index (IRQn + 16)  

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  • 0 in reply to DFinn

    Chapter 7 has an example of setting up interrupts right in the chapter as well as an English description of what it is doing.  (Page 268 of the 3rd edition has a "simple" setting up of an interrupt example. )

    It goes like this 

    // No need to set priority grouping just yet, use the default

    // No need to set the priority just yet, use the default

    NVIC_EnableIRQ(IRQn);

    If you want to execute this interrupt through software

    NVIC_SetPendingIRQ(IRQn);

    Normally the hardware would assert the interrupt pending and not the software, but this would let you test the IRQ out.

    When the Interrupt happens the processor will enter the Exception sequence ending with loading the PC with the address in the Vector Table at index (IRQn + 16)  

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