I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.
Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will the M0+ handle it (which only does reduced thumb2)? If not, which comparable?
What I find confuses me. In a thumb2 ref card I found that "Width of bitfield. <width> + <lsb> must be <= 32." But some 5 years ago I programmed some on a STR91xF ARM9 processor, and there was some talk about l-o-n-g bit arrays that could be handled in one cycle, but there was some 1024 bytes of microcoded table for this. (See, I am already long afloat, in deep water! Maybe this was for all kind of masks?)
Also, what would happen if I need to set or clear (like) bit 27 and bit 60 in one instruction? Will compilers (which?) then treat a full 32 bits word times two, a 64 bits word, or will it handle only byte 3 and byte 7 (starting at byte 0) and do the trick on them? Is the barrel shifter part of this?
Aclassifier
Øyvind Teig | Some of my blog notes
aclassifier wrote: In a thumb2 ref card I found that "Width of bitfield. <width> + <lsb> must be <= 32."
aclassifier wrote:
In a thumb2 ref card I found that "Width of bitfield. <width> + <lsb> must be <= 32."
This means that the bit-field instructions on Cortex-M devices can not handle bit operations larger than 32 bit.
It also means that you can't 'wrap' bit fields, so the following...
ubfx r0,r1,#24,#16
... will not be valid. You would probably expect (like I did) that the above instruction would copy the top 8 bits of r1 to the bottom 8 bits of r0 and the bottom 8 bits of r1 to bits 15:8 of r0. But the instruction is invalid, because the combination of the start and length parameters do not exist, thus there is no opcode available for an instruction with those parameters.
It is possible to do the operation using a different approach, though:
movw r7,#0xffff
ands r0,r7,r1,ror#24
-And of course, it would pay to reuse r7 if more bit fields of this kind needs to be extracted.
The above example is using the barrel-shifter; this is present on Cortex-M3 and later, but isn't available on Cortex-M0 (due to the limited number of opcodes).