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How long bitfields on which ARM?

I need to be able to handle long bitfields as effectively as possible. Right now I need up to 64 bits in length.

Are there instructions to set, clear and test individual bits in one cycle available for some of the architectures? Which? Particularly, will the M0+ handle it (which only does reduced thumb2)? If not, which comparable?

What I find confuses me. In a thumb2 ref card I found that "Width of bitfield. <width> + <lsb> must be <= 32." But some 5 years ago I programmed some on a STR91xF ARM9 processor, and there was some talk about l-o-n-g bit arrays that could be handled in one cycle, but there was some 1024 bytes of microcoded table for this. (See, I am already long afloat, in deep water! Maybe this was for all kind of masks?)

Also, what would happen if I need to set or clear (like) bit 27 and bit 60 in one instruction? Will compilers (which?) then treat a full 32 bits word times two, a 64 bits word, or will it handle only byte 3 and byte 7 (starting at byte 0) and do the trick on them? Is the barrel shifter part of this?

Aclassifier

Øyvind Teig | Some of my blog notes

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  • Hi Aclassifier,


    if you use a C compiler you can handle up to 64bit width fields by using the long long integer type.
    For example please look at the following example. If you would use an assembler you would have many options as was mentioned. The limitation of the bitfield instruction comes from the fact it can process 32bit data at one time.

    [source code]

    union {
    char a[10];
    long long b:64;
    } X;

    main()
    {
       X.b=0x0123456789abcdefLL;
    }

    [disasseble code]

    00000000 <main>:
       0:   b510            push    {r4, lr}
       2:   4a03            ldr     r2, [pc, #12]   (10 <main+0x10>)
       4:   4b03            ldr     r3, [pc, #12]   (14 <main+0x14>)
       6:   4c04            ldr     r4, [pc, #16]   (18 <main+0x18>)
       8:   6013            str     r3, [r2, #0]
       a:   6054            str     r4, [r2, #4]
       c:   bd10            pop     {r4, pc}
       e:   46c0            nop                     (mov r8, r8)
      10:   00000000        .word   0x00000000
      14:   89abcdef        .word   0x89abcdef
      18:   01234567        .word   0x01234567

    Best regards,
    Yasuhiko Koumoto.

Reply
  • Hi Aclassifier,


    if you use a C compiler you can handle up to 64bit width fields by using the long long integer type.
    For example please look at the following example. If you would use an assembler you would have many options as was mentioned. The limitation of the bitfield instruction comes from the fact it can process 32bit data at one time.

    [source code]

    union {
    char a[10];
    long long b:64;
    } X;

    main()
    {
       X.b=0x0123456789abcdefLL;
    }

    [disasseble code]

    00000000 <main>:
       0:   b510            push    {r4, lr}
       2:   4a03            ldr     r2, [pc, #12]   (10 <main+0x10>)
       4:   4b03            ldr     r3, [pc, #12]   (14 <main+0x14>)
       6:   4c04            ldr     r4, [pc, #16]   (18 <main+0x18>)
       8:   6013            str     r3, [r2, #0]
       a:   6054            str     r4, [r2, #4]
       c:   bd10            pop     {r4, pc}
       e:   46c0            nop                     (mov r8, r8)
      10:   00000000        .word   0x00000000
      14:   89abcdef        .word   0x89abcdef
      18:   01234567        .word   0x01234567

    Best regards,
    Yasuhiko Koumoto.

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