Hi,
I have been reading about the exception mechanism of Cortex-M (M4 to be precise). The exception request is accepted by the processor if the current priority level of the processor is less than the incoming exception (this is one of the conditions to accept the request). So I am a bit confused about what is meant by 'Current priority level of processor'. I can guess that when the processor is in handler mode, it will be the priority level of that exception. But when the processor is in thread mode, say just running a normal user program after reset, what is the priority level of the processor?
Thanks,
Gopal
I think you need a newer version of the reference manual. I see the wording you quoted in the SAM3X8 datasheet, but NOT in either the current ARMv6m or ARMv7m Architecture Reference Manuals. (ie https://developer.arm.com/documentation/ddi0403/d/System-Level-Architecture/System-Level-Programmers--Model/Registers/The-special-purpose-mask-registers )
Those are also clear in the MSR instruction definition that it copies the low order bit of the specified register to the PRIMASK.PM bit.