• State Accepted Answer
  • Locked Locked
  • Replies 3 replies
  • Subscribers 349 subscribers
  • Views 22593 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

A35 Power Mode Transitions

EricDobbins

Has anyone come across documentation that tells how to calculate entrance and exit times from low-power modes where the L1 and L2 cache maintain data coherence?

Thanks,

Eric

Parents
  • 0 in reply to EricDobbins

    Even saying you are using an A35 does not help more. Each SoC is different.
    I wonder, do you fear a competitor will read your post if you disclose the chip you are using?
    Anyway,  some SoC manuals tell you about how many cycles the PLL needs to lock and things like this.
    And if not the manual, then the chip-vendor might tell you.
    But the core is the smallest part on your SoC, so the ARM (core) forum will be of little help.

Reply
  • 0 in reply to EricDobbins

    Even saying you are using an A35 does not help more. Each SoC is different.
    I wonder, do you fear a competitor will read your post if you disclose the chip you are using?
    Anyway,  some SoC manuals tell you about how many cycles the PLL needs to lock and things like this.
    And if not the manual, then the chip-vendor might tell you.
    But the core is the smallest part on your SoC, so the ARM (core) forum will be of little help.

Children
No data