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Hi All,
In R4 trm, there are some words about low interrupt latency. I have a question about it.
" Low interrupt latency
On receipt of an interrupt, the processor abandons any pending restartable memory operations.
Restartable memory operations are the multiword transfer instructions LDM, LDRD, STRD, STM, PUSH,
and POP that can access Normal memory.
To minimize the interrupt latency, ARM recommends that you do not perform:
• multiple accesses to areas of memory marked as Device or Strongly-ordered
• SWP operations to slow areas of memory."
My question is that:
Suppose I use the LDM instruction and this causes a cache miss, and this cache miss triggers line fill which take forever. This hangs my cpu. So my cpu cannot respond any more. In this case, will IRQ/FIQ trigger the cpu to abandon this LDM? If yes, what kind of special configuration I need. Thanks.
Best,
Patrick
I see you're talking about loading a cache line in an abandoned LDM.. By hang do you mean the time to load a cache line from memory and that the processor is slowed down by that, or do you mean the processor actually does hang and does not continue execution?
If one is worried by that time and have to have a low latency interrupt then one needs to use Tightly Coupled Memory for everything the critical interrupt handler uses.
The problem as I see it then is whether a cache line fill for the abandoned LDM will interfere with a device access using STR. I don't know the answer to that, presumably it depends on the implementation.I suppose it is possible. Also a device access will complete rather than be abandoned if an interrupt happens during one which could also affect the interrupt latency.