Hi All,
In R4 trm, there are some words about low interrupt latency. I have a question about it.
" Low interrupt latency
On receipt of an interrupt, the processor abandons any pending restartable memory operations.
Restartable memory operations are the multiword transfer instructions LDM, LDRD, STRD, STM, PUSH,
and POP that can access Normal memory.
To minimize the interrupt latency, ARM recommends that you do not perform:
• multiple accesses to areas of memory marked as Device or Strongly-ordered
• SWP operations to slow areas of memory."
My question is that:
Suppose I use the LDM instruction and this causes a cache miss, and this cache miss triggers line fill which take forever. This hangs my cpu. So my cpu cannot respond any more. In this case, will IRQ/FIQ trigger the cpu to abandon this LDM? If yes, what kind of special configuration I need. Thanks.
Best,
Patrick
Hi Patrick,
when you say you did some simulation, are you simulating RTL, or is this on a model? What sort of memory is the store going to? (ie just checking it's not on a TCM interface). Even if it's to normal memory, it could be ending up in the cache depending on whether you have write-through or write-back mode configured. Just trying to make sure I've got a full picture of your system.
regards,
Jon