The processor is Samsung's Exynos 4210, ARM Cortex-A9, I want to know whether it supports the L2 cache refill or memory access event?
There are some hit and miss counters in the PL310 TRM (section 2.5.8 in the PDF, which I find easier to read than the online docs).
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246h/CHDGJFHA.html
However, access may be restricted - I'm not sure how the cache debug pins are wired on the Exynos 4210.
HTH, Pete
Thank you for your reply,I got what I want.
But only two event counter are used at a time.....Can I record more L2-cache events?