Hi, I'm new to community.
I am recently working on cache performance evaluation of a software on arm ( which I did not know much about before) and aiming to record all the instructions causing a data cache miss.
Currently, my way is straightforward: I configure the PMUIRQ as FIQ and set counter to -1 initially, and every time a overflow FIQ occurs the handler will first disable cache, disable counter, push lr to a stack, reset counter to -1, enable counter, enable cache again and return to lr - 4.
But from the lr I record, I found many of the cache-miss instructions( which are lr - 8 ) do not access data in memory (like branch, cmp, etc).
I want to ask:
1. Which instructions are possible to cause a cache miss ?
2. Is that possible that the FIQ request is delayed ?
3. Is there any better idea to record the cache-miss instructions?
Thank you!