I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.
The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
The ICI bits at the time of the interrupt equal 7. This means that the STM was partially completed, and should be resumed starting at r7.
However, if I look at the stack at the time of the interrupt, I see 4 words were written by the interrupted STM, namely r4, r5, r6, and r7. This means that
r7 will be written again when the processor resumes the STMDB instruction.
This does not happen all the time. But it forces me to disable interruption of multicycle instructions.
Hi paulgiangrossi,
you wrote that you used this instruction: STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}.In case of STMDB the accesses happen in order of decreasing register numbers. There is a rule, that the highest numbered register is always placed to the highest memory address and so on. (According to this rule your instruction is the same that for example: STMDB sp!, {r7-r9, lr, r5-r6, sl, r4})I think that actually lr, sl, r9 and r8 were stacked. The next register in the decreasing queue is r7 which is correctly stored in the ICI bits.
Could it happen that you didn't compared your registers with your stack precisely?