I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions.
The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
The ICI bits at the time of the interrupt equal 7. This means that the STM was partially completed, and should be resumed starting at r7.
However, if I look at the stack at the time of the interrupt, I see 4 words were written by the interrupted STM, namely r4, r5, r6, and r7. This means that
r7 will be written again when the processor resumes the STMDB instruction.
This does not happen all the time. But it forces me to disable interruption of multicycle instructions.
Hi paulgiangrossi,
please tell me a detailed conclusion of this problem. I am very interested in it. As the results, was it a bug?
Best regards,Yasuhiko Koumoto.
Hi Yasuhiko,
We are still investigating. I will publish results once we have
determined what the problem is.
Best,
Paul Giangrossi
Unable to reproduce this problem in RTL simulation. It is reproducible
on an FPGA prototype. The project resolution is to disable multi-cycle
instruction interrupts via the Auxiliary Control Register.
The ARM support case is closed. It is most likely something with our
implementation.
I've not seen a close to
about some R4 problem which may be similar. Well I'm not sure what on earth is happening there really but if it really does boil down to the same thing then there's some bug which hasnt been winkled out yet.
let me confirm that your RTL simulation was done with the FPGA model including the bus system? Like daith, I have a suspicion the system bus (e.g. AHB?) of FPGA might have some troubles.