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Hi All,
I could understand the difference in ARM V-7 processor differences between A/R/M.
But does the clock cycle per instruction value for the various series of processors (A/R/M) remains the same or similar, assuming the data fetch and instruction fetch can be made in a single clock (say from cache) ?
Is there any white paper document discussing on it ?
What is the similarity between ARM V-7 processors ?
Hi,
you could find the information on the book is ARM System-on-chip Architecture by Prof Steve Furber.
Yes, Steve Furber's excellent book does provide some of this information. But only in relation to really quite old ARM technology and products.
For the newer products, you need to look in the Technical Reference Manual for each core. This will give information about cycle timing, pipeline behaviour etc. Please be aware, though, that they do not tell the whole story. In order to protect our IP, we do not release full details of the internal microarchitecture of our implementations.
To answer your question, yes cycle timing does change from core to core. Many things stay the same (almost all implementations, for instance, will execute an ADD instruction in a single cycle) but many things change due to differences in pipeline structure and optimizations like register renaming, speculative execution and so on. In the case of the later cores, it actually becomes less and less useful to publish this information as the pipelines are so complex that they are almost impossible to analyse by hand.
Hope this helps
Chris
Thank you shufan.
Hi Chris,
Your description provides me the detailed picture.
Regards,
Techguyz