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About AXI4 address channel and data channel handshake sequence

I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

Remark:

Just now, I noticed that,  "AMBA AXI and ACE Protocol Specification" says:

"read data must always follow the address to which the data relates" and

"This means, for example, the write data can appear at an interface before the write address for the transaction"

I suppose this is the answer

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