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I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?
For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?
Remark:
Just now, I noticed that, "AMBA AXI and ACE Protocol Specification" says:
"read data must always follow the address to which the data relates" and
"This means, for example, the write data can appear at an interface before the write address for the transaction"
I suppose this is the answer
I assume you were reading ARM IHI 0022E document for AXI4 protocol. At page A3-43 you may find read transaction handshake dependencies: "the slave must wait for both ARVALID and ARREADY to be asserted before it asserts RVALID to indicate that valid data is available", and "the master can assert RREADY before RVALID is asserted". Hence it is possible to assert RREADY before ARVALID/ARREADY and wait till RVALID asserted to complete the read data channel handshake.
Regarding write transaction, the WVALID/WREADY signals can be asserted before or after AWVALID/AWREADY, while on the write response channel the slave MUST wait for AWVALID/AWREADY, WVALID/WREADY and WLAST to be asserted BEFORE asserting BVALID.
Regards,
Xiaotao