From the specification exert below, I understand, that setting FIFO enable to 1, enables also the DMA Mode. Does it mean the DMA Mode operates "automatically"? I cannot see a relationship, that I have to configure the DMA in some way. In other ways, how should I read the below specification regarding operating or not with DMA?
"UARTn FIFO Control Register Bit Symbol 0 FIFO Enable 1 Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs. 3 DMA Mode 1 When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode 4.6.1 DMA OperationThe user can optionally operate the UART transmit and/or receive using DMA. The DMAmode is determined by the DMA Mode Select bit in the FCR register. This bit only has anaffect when the FIFOs are enabled via the FIFO Enable bit in the FCR register. UART receiver DMA In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFOlevel becoming equal to or greater than trigger level, or if a character timeout occurs." UM10360LPC17xx User manualRev. 01 — 4 January 2010
"UARTn FIFO Control Register
Bit Symbol
0 FIFO Enable 1 Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs.
3 DMA Mode 1 When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode
4.6.1 DMA OperationThe user can optionally operate the UART transmit and/or receive using DMA. The DMAmode is determined by the DMA Mode Select bit in the FCR register. This bit only has anaffect when the FIFOs are enabled via the FIFO Enable bit in the FCR register.
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFOlevel becoming equal to or greater than trigger level, or if a character timeout occurs."
UM10360LPC17xx User manualRev. 01 — 4 January 2010
ArmAsking said:the question is about interpreting the specification
But that has nothing to do with ARM: it is NXP's IP, and NXP's specification - so you need to ask NXP for any clarification of their documentation.
https://community.nxp.com/
For the distinction between what;s ARM's and what is the chipmaker's, See:
https://community.arm.com/developer/tools-software/tools/f/keil-forum/43684/lpc2148-timer0-not-working-as-expected/158950#158950