• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 8 replies
  • Subscribers 352 subscribers
  • Views 13101 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex-R5: Divide-by-zero

Tau

Hello,

I am using Xilinx MpSoc Ultrascale+ ZCU102.

I want to generate an interrupt when dividing by zero.
I read the Cortex-R5 technical reference manual (infocenter.arm.com/.../index.jsp
The system control register C1 has the DZ bit which control the generation of Undefined Instruction exception.

My SW is running as a standalone on R5-0.
The file xreg_cortexr5.h consists the XREG_CP15_CONTROL (the C1 Register Defines) but the DZ bit is not exist there.

When I tried to change this bit by myself (using inline assembler code) according to the ARM Cortex-R5 details mentioned above and handle this with my own function, I got a SW interrupt in every cycle of my application.

Why the DZ bit is not appear in xreg_cortexr5.h?
Why changing its value cause a SW interrupt?

Is there a different way to generate the divide by zero interrupt?

Thanks!

0