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Exception / Interrupt for Cortex-A15

Hi,

I would like to know whether my understanding is right or not regarding to the interrupt (exception).

When an interrupt is issued, the interrupt is executed at once without the completeion of the executing instrructions.

And, the contents of the result queue is discarded.

After the interrupt execution is completed, all instructions that was included in result queue is executed again without refetch instructions.

If my understanding is right,  which area is all feteched instructions stored for re-execution after return from the exception?

I appreciate your quick reply.

Best regards,

Michi

Parents
  • The processors state when you enter the ISR must be as if the previous instruction had fully finished executing, you cannot take an interrupt in the middle of an instruction.

    Running the ISR will cause an effective pipeline flush as the interrupted instructions must make way to execute the ISR's instructions.  The previous instructions can remain in the instruction cache (assuming they are in cacheable memory.)  When you return from the exception you will need to re-fetch those instructions but you may hit in the cache, therefore you may not see any bus traffic,

Reply
  • The processors state when you enter the ISR must be as if the previous instruction had fully finished executing, you cannot take an interrupt in the middle of an instruction.

    Running the ISR will cause an effective pipeline flush as the interrupted instructions must make way to execute the ISR's instructions.  The previous instructions can remain in the instruction cache (assuming they are in cacheable memory.)  When you return from the exception you will need to re-fetch those instructions but you may hit in the cache, therefore you may not see any bus traffic,

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