As above~
Hi Jay,
Thanks for your question.
Could you please describ your question more detail?
As the experts need more information to understand it.
Thanks,
Ben
Hi Song,
Thank u for replying.
My question is that when my chip is running in secure mode (trustzone for ARM), and I operate the coprocessor (No.15) trying to switch the ARM mode to Trustzone, i.e., secure mode, will that lead to some kind of abort or exception, I'm doing this because I don't know which mode my chip is in.
So I mean, does ARM core respond to such redundancy operates with some mechanisms to inform me that the chip is already in secure mode.
Best Regards
Jay
Understand, please let me move your question to ARM Processors Group, there will be experts can help you.
You can join that group and enjoy the discussion.
My question is that when my chip is running in secure mode (trustzone for ARM), and I operate the coprocessor (No.15) trying to switch the ARM mode to Trustzone, i.e., secure mode, will that lead to some kind of abort or exception, I'm doing this because I don't know which mode my chip is in. So I mean, does ARM core respond to such redundancy operates with some mechanisms to inform me that the chip is already in secure mode.
Switching worlds directly via the NS bit in CP15 is not recommended, as it is an unmanaged world change. It is recommended that privileged code executes an SMC instruction to cause a transition via the monitor mode / monitor code which manages safe state safe/restore.
HTH, Pete
Will SMC instruction directly cause the transition via monitor mode, or I should use a switch routine to handle the smi_hdler exception to finish the transition?
You'll need some monitor mode software to handle the exception - there's no automatic hardware support (i.e. it behaves like any other svc software "interrupt").
Thank u very much~