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C/C++ atomic operation on ARM9 and ARM Cortex-M4

John

I have a question about C/C++ atomic operation on ARM9 and ARM Cortex-M4. I am using ARMCC compiler with C / C++ languages. It interests me if it is possible that an interrupt will be handled in the middle of operations:

  • Read 8-bit character form structure which is not aligned (packed).  From internal memory.
  • Read 8-bit character form structure which is not aligned (packed).  From external memory.
  • Read 32-bit integer from external memory. The memory is connected to the processor by 16 (or 8) bits data line.
  • Read 64-bit long long integer from internal memory.
  • Read 64-bit long long integer from external memory.

Does anything change if you access to these objects indirectly by pointer or reference?

Are there any other basic operations potentially unsafe in multi-thread application?

Thanks for answers.

Parents
  • 0 Arm Employee Badge in reply to Carlos Delfino

    Hi Carlos,

    Sorry that I forgot to specify that the LDM/STM resume behavior is for ARMV7-M, where ICI/IT bits present in xPSR. (ie Cortex-M3/M4/M7). For ARMv6-M (Cortex-M0/M0+), the LDM/STM are abandoned and restarted after interrupt service.

    There are no LDRD/STRD instructions in ARMv6-M.

    Regards,

    Joseph

    Sent from Samsung Mobile

Reply
  • 0 Arm Employee Badge in reply to Carlos Delfino

    Hi Carlos,

    Sorry that I forgot to specify that the LDM/STM resume behavior is for ARMV7-M, where ICI/IT bits present in xPSR. (ie Cortex-M3/M4/M7). For ARMv6-M (Cortex-M0/M0+), the LDM/STM are abandoned and restarted after interrupt service.

    There are no LDRD/STRD instructions in ARMv6-M.

    Regards,

    Joseph

    Sent from Samsung Mobile

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