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C/C++ atomic operation on ARM9 and ARM Cortex-M4

John

I have a question about C/C++ atomic operation on ARM9 and ARM Cortex-M4. I am using ARMCC compiler with C / C++ languages. It interests me if it is possible that an interrupt will be handled in the middle of operations:

  • Read 8-bit character form structure which is not aligned (packed).  From internal memory.
  • Read 8-bit character form structure which is not aligned (packed).  From external memory.
  • Read 32-bit integer from external memory. The memory is connected to the processor by 16 (or 8) bits data line.
  • Read 64-bit long long integer from internal memory.
  • Read 64-bit long long integer from external memory.

Does anything change if you access to these objects indirectly by pointer or reference?

Are there any other basic operations potentially unsafe in multi-thread application?

Thanks for answers.

Parents
  • 0

    Hi and welcome to the community.

    I do not know much about ARM9, but I can say that on Cortex-M4, an interrupt can occur between every memory read or memory write.

    This includes the LDM and STM instructions.

    The LDM/STM instructions will be interrupted, and when the interrupt returns, the LDM or STM instruction will continue from where they left off.

    -It does not make any difference whether the memory is internal or external; the memory can be internal SRAM, external SRAM or external SDRAM, even I/O-space (hardware registers).

    The 64-bit long integers will go into two 32-bit integer registers, so they will also be read as two 32-bit values separately.

    So I believe your only bet is to use the Load Exclusive and Store Exclusive to create semaphores or access counters/indexes.

    There are C inline functions available for your Cortex-M4 for this, see the core_cmInstr.h file for details.

    Some of the inline functions you may be interested in are:

    • __LDREXB(addr)
    • __LDREXH(addr)
    • __LDREXW(addr)
    • __STREXB(value, addr)
    • __STREXH(value, addr)
    • __STREXW(value, addr)

    For technical details on these functions, you can find the actual assembly-language instructions here:

    ARM Information Center

Reply
  • 0

    Hi and welcome to the community.

    I do not know much about ARM9, but I can say that on Cortex-M4, an interrupt can occur between every memory read or memory write.

    This includes the LDM and STM instructions.

    The LDM/STM instructions will be interrupted, and when the interrupt returns, the LDM or STM instruction will continue from where they left off.

    -It does not make any difference whether the memory is internal or external; the memory can be internal SRAM, external SRAM or external SDRAM, even I/O-space (hardware registers).

    The 64-bit long integers will go into two 32-bit integer registers, so they will also be read as two 32-bit values separately.

    So I believe your only bet is to use the Load Exclusive and Store Exclusive to create semaphores or access counters/indexes.

    There are C inline functions available for your Cortex-M4 for this, see the core_cmInstr.h file for details.

    Some of the inline functions you may be interested in are:

    • __LDREXB(addr)
    • __LDREXH(addr)
    • __LDREXW(addr)
    • __STREXB(value, addr)
    • __STREXH(value, addr)
    • __STREXW(value, addr)

    For technical details on these functions, you can find the actual assembly-language instructions here:

    ARM Information Center

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