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Cortex-M4 interrupts behaviour when same interrupt vector has multiple interrupts

Hello,


I am using STM32F407ZGT6 Cortex-M4 microcontroller. This controller has same interrupt vector for 5 external interrupts i.e., NVIC (EXTI9_5) for EXTI5, EXTI6, EXTI7, EXTI8 and EXTI9 interrupts. They all have the same ISR EXTI9_5_IRQHandler interrupt service routine. So, one has to check the independent flags of each external interrupt to determine the source of the interrupt.

I am confused about how the service routine is called in case multiple interrupts arrived. Lets say, an interrupt due to EXTI5 has arrived, its interrupt handler is called and the interrupt is servicing. Meanwhile, EXTI6 interrupt is detected. Now, will the interrupt handler be called again when the EXTI5 interrupt is fully serviced or since it is already in the interrupt handler, it will not be called again?

In short, which method should I write among the following two styles:

void EXTI9_5_IRQHandler (void)

{

     if EXTI5 happens

     {

          EXTI5 ISR

     }

     if EXTI6 happens

     {

          EXTI6 ISR

     }

     if EXTI7 happens

     {

          EXTI7 ISR

     }

     if EXTI8 happens

     {

          EXTI8 ISR

     }

     if EXTI9 happens

     {

          EXTI9 ISR

     }

}

OR

void EXTI9_5_IRQHandler (void)

{

     if EXTI5 happens

     {

          EXTI5 ISR

     }

     else if EXTI6 happens

     {

          EXTI6 ISR

     }

     else if EXTI7 happens

     {

          EXTI7 ISR

     }

     else if EXTI8 happens

     {

          EXTI8 ISR

     }

     else if EXTI9 happens

     {

          EXTI9 ISR

     }

}

Thanking in anticipation for your time and help.

Parents
  • Hi Jens ,

    In this case, EXTI5, 6, 7, 8, 9 all sharing one input pin on the NVIC.

    The STM32's External Interrupt/Event Controller (EXTI) module should be designed to general interrupt request in form of level (rather than pulse). Also, the EXTI module have its own interrupt pending status register for each of the pin. The interrupt requests are merged using an OR function before connecting to the NVIC. (Note: this is specific to STM32 design).

    Each of the interrupt service (for each EXTI channel) need to clear their own pending status in the EXTI using EXTI_PR (pending register) to deassert the interrupt to NVIC. If another EXTI is pending, the clearing of the pending status in EXTI is not going to deassert the interrupt line, so the same IRQ will be triggered again and get serviced when the first ISR exited.

    Both coding styles should work. But the first one works better (lower overhead) when multiple EXTI interrupts arrive at the same time because it can service multiple EXTI requests in the same ISR execution. The second coding style means it need to exit the ISR, then get back to it again and service the another EXTI request.

    regards,

    Joseph

Reply
  • Hi Jens ,

    In this case, EXTI5, 6, 7, 8, 9 all sharing one input pin on the NVIC.

    The STM32's External Interrupt/Event Controller (EXTI) module should be designed to general interrupt request in form of level (rather than pulse). Also, the EXTI module have its own interrupt pending status register for each of the pin. The interrupt requests are merged using an OR function before connecting to the NVIC. (Note: this is specific to STM32 design).

    Each of the interrupt service (for each EXTI channel) need to clear their own pending status in the EXTI using EXTI_PR (pending register) to deassert the interrupt to NVIC. If another EXTI is pending, the clearing of the pending status in EXTI is not going to deassert the interrupt line, so the same IRQ will be triggered again and get serviced when the first ISR exited.

    Both coding styles should work. But the first one works better (lower overhead) when multiple EXTI interrupts arrive at the same time because it can service multiple EXTI requests in the same ISR execution. The second coding style means it need to exit the ISR, then get back to it again and service the another EXTI request.

    regards,

    Joseph

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