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Secure world entry request by normal world application

Shane Yu

For a TrustZone enabled processor, what if a normal world application (e.g. 3rd party application) directly uses SMC instruction to request a secure world entry? In a typical case, it it a responsibility of monitor SW or Secure OS kernel to authenticate the request? Thanks!

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  • 0 in reply to Martin Weidmann

    Thanks a lot Martin!

    I checked the description from "Cortex-A9 Technical Reference Manual" Revision: r4p1, in page 4-6 (pdf page 55). I found the SCR register is short for "Secure Configuration Register", and its NS bit (0th bit, non-secure bit) is used to show whether the system is in the secure or the non-secure world. This SCR register belongs to CP15 C1 registers.

    In the manual after the term of SCR, there are two superscript notes, one says, "No access in Non-secure state.", another says "SCR[6] is not implemented, RAZ/WI.".

    However, in the "Cortex-A5 Technical Reference Manual" Revision: r0p1, in page 4-15 (pdf page 64), there is no such superscript note shows the SCR register is not implemented(indicating the SCR is implemented in Cortex-A5?).

    Yesterday, with the Cortex-A9 MCU (i.MX6Solo), I tried to read out the value of SCR register in CP15 C1, and the value was 0x00000000. The NS bit (0th bit, non-secure bit) was 0, I am not sure whether the system was in the secure world or not.

    Thanks a lot again!

Reply
  • 0 in reply to Martin Weidmann

    Thanks a lot Martin!

    I checked the description from "Cortex-A9 Technical Reference Manual" Revision: r4p1, in page 4-6 (pdf page 55). I found the SCR register is short for "Secure Configuration Register", and its NS bit (0th bit, non-secure bit) is used to show whether the system is in the secure or the non-secure world. This SCR register belongs to CP15 C1 registers.

    In the manual after the term of SCR, there are two superscript notes, one says, "No access in Non-secure state.", another says "SCR[6] is not implemented, RAZ/WI.".

    However, in the "Cortex-A5 Technical Reference Manual" Revision: r0p1, in page 4-15 (pdf page 64), there is no such superscript note shows the SCR register is not implemented(indicating the SCR is implemented in Cortex-A5?).

    Yesterday, with the Cortex-A9 MCU (i.MX6Solo), I tried to read out the value of SCR register in CP15 C1, and the value was 0x00000000. The NS bit (0th bit, non-secure bit) was 0, I am not sure whether the system was in the secure world or not.

    Thanks a lot again!

Children
  • 0 Arm Employee Badge in reply to Rui

    In the manual after the term of SCR, there are two superscript notes, one says, "No access in Non-secure state.", another says "SCR[6] is not implemented, RAZ/WI.".

    However, in the "Cortex-A5 Technical Reference Manual" Revision: r0p1, in page 4-15 (pdf page 64), there is no such superscript note shows the SCR register is not implemented(indicating the SCR is implemented in Cortex-A5?).

    The SCR will be present on all ARMv7-A processors that implement the Security extensions.  This includes the Cortex-A5 and Cortex-A9. 

    Yesterday, with the Cortex-A9 MCU (i.MX6Solo), I tried to read out the value of SCR register in CP15 C1, and the value was 0x00000000. The NS bit (0th bit, non-secure bit) was 0, I am not sure whether the system was in the secure world or not.

    The SCR is Secure access only.  Attempting to read it from Non-secure state will result in an Undefined Instruction exception.  So if you are able to read it successfully, you can infer you must be in Secure state.

  • 0 in reply to Martin Weidmann

    Great! This is very helpful, Thank you Martin!