Cortex-M0DS Kit computing power and interfacing

Greeting of the day
Hello. My name is Ketan. I've been recently granted access to the design start kit for the Cortex-M0DS processor.I also downloaded some examples design from ARM website which interfaces AMBA bus with Cortex-M0DS processer( link of examples http://www.arm.com/files/zip/CM0DS-DesignKit.zip).

I already interface AHB2LED,AHB2MEM_V2,AHB2GPIO,AHB2UART WITH CORTEX-M0DS processor and implemented it on Atlys Spartan-6 FPGA board (link for board Digilent Inc. - Digital Design Engineer's Source ) and it is working fine. I am currently facing the following problem which i am unable to figure it out for that I need some guidance.

1. I need to process two signal which we are taking through ADC, do digital filtering and feature extraction(peak detection - and to take the result using UART to host PC for that i already implemented all parameter and I am unable to figure out about ADC ip core(as it contain both analog and digital part).
2. The FPGA board i am using does not have cellular RAM and parallel flash insted it has 128Mbyte DDR2 memory array for that purpose I need to implement DDR2 memory controller.
3. And third question, is there is any standard procedure to find out whether Cortex-M0DS (limited functionality wrt actual Cortex-M0) processor is suitable for my application or not (i.e Cortex-M0 has enough computing power for my application or not). As my application is aquaring two analog signals(around 100 hz frequency)  and do digital filtering and feature extraction (peak detection) from the signal. [I already test the code on Cortex-M3 processor in a kit LPC1768 and it is working fine].