ARMv5 Instruction Cycle Summary?

You mean ARMv5 / ARMv5TE?  If so, "ARMv5" is a version of the architecture.  The ARM Architecture is essentially a functional specification - it wouldn't define cycle timings.

Cycle timings come from the specific implementation.  For example, ARM946E-S, is a processor that implements ARMv5TE.  The cycle timings come from the processor design (such as it's pipeline design).  If you took a different ARMv5TE processor it could have different timings.

The document you linked to is the figures for the ARM9E-S family of processors.  I think this probably what you want.

NOTE: The figures the doc gives are independent of the memory system.  That is, you might also need to consider things like cache mit/misses and memory timings.

You mean ARMv5 / ARMv5TE?  If so, "ARMv5" is a version of the architecture.  The ARM Architecture is essentially a functional specification - it wouldn't define cycle timings.

Cycle timings come from the specific implementation.  For example, ARM946E-S, is a processor that implements ARMv5TE.  The cycle timings come from the processor design (such as it's pipeline design).  If you took a different ARMv5TE processor it could have different timings.

The document you linked to is the figures for the ARM9E-S family of processors.  I think this probably what you want.

NOTE: The figures the doc gives are independent of the memory system.  That is, you might also need to consider things like cache mit/misses and memory timings.