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Hello.I downloaded the ARMv6 manual and there are a few things that I don't understand."For an ARM instruction, the value read [from the program counter] is the adress of the instruction plus 8 bytes. Bits [1:0] of this value are always zero, because ARM instructions are always word-aligned."So why it is "the adress + 8"? If the instruction has 4 bytes, it would be the "next next" instruction, wouldn't it?And which bits are the [1:0]? (Could you show me in a manner like this: 11010001b ?)And the phrase right below the previous one:
"For a Thumb instruction set, the value read is the adress of the instruction plus 4 bytes. Bit [0] of this value is always zero, because Thumb instructions are always halfword-aligned."
Again, why "adress plus 4" and what is the "Bit [0]".Thanks for reading.
The address+8 is a bit of cruft from the original ARM design. It pipelined Fetch, Decode, Execute. During Execute the Fetch address would be that of the current address+8.
Bits 1 and 0 are the zeroes in ....11111100b.
Bit 0 for Thumb is the zero in ....1111110b, however note that if you want to use that as a thumb address in BX or BLX that bit needs to be 1 otherwise it switches to ARM mode. Thumb code addresses will normally have bit 0 set to 1.
I'm sorry but I'm a beginner with the ARM technology. I can't just imagine that. The adress is different between some passes in the pipeline?!Could you describe it better in a step-by-step like manner?Thanks for reading.
*One off-topic question: This makes me really thinkt that I'm ********. It is said that Branch instructions in ARM mode contain a 24-bit signed word offset and with this offset it can move forward and backward of up to 32MB. What is the calculation to get 32 MB from 24-bit signed offset?
Have a look at a diagram of a simple classical pipeline on WIkipedia at
https://en.wikipedia.org/wiki/Classic_RISC_pipeline
if the execute stage uses the address of the instruction being fetched in the fetch stage then the value used will be the pc of the instruction being executed plus 8
The address of a 32 bit ARM instructions always has the last two bits zero so they don't have to be specified in a branch instruction. The 24 bit literal is multiplied by 4 to give the displacement to be added to the pc value.