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Cortex-M pipeline, relationship prefetch and decode stages

Hi ARM specialists,

I have a question about Cortex-M series pipeline behavior.

According to the page 15 of "ARM Cortex-M Programming Guide to Memory Barrier Instructions Application Note 321", it is described that "Instruction fetch can happen several cycles before decode and execution". If fetch, decode. and execution stages are synchronized, the decode and execution stages would take the same cycles as the fetch stage. If it is true, the long prefetch (or fetch) stage makes performance lower. I think that the prefetch and decode stages are decoupled because the above assumption would be strange.

Is it true? I would like to know the relationship between the prefetch and decode stages of Cortex-M0/M0+/M3/M4. That is, would the prefetch stage latency affect the following stages or not?

Yasuhiko Koumoto.

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