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1. I'm examining AXI burst of FIXED type.
2. Data bus width is of 128bit.
3. case scenario WRITE:
awlen = 2 (3 write transfers)
awsize = 2 (32bit per each transfer)
awburst = 0 (FIXED)
awaddr = 0x6116_0304;
4. wrstrb(write strobe) values throughout the burst (a total of 3 transfers): 0x00f0, 0x00f0, 0x00f0
(Usually FIXED burst type will be used for writing into a FIFO).
5. first question:
The wrstrb is fixed, this means that per transfer the Master convey the same 32bit data location ---> 32 32 32 32 (a total of 128bits per transfer).
msb lsb
Assuming that the Master takes the data from a memory location, the Slave receives a non consecutive data...
I mean: Assume the following memory address space (per address location you have 4bytes, 32bits):
first transfer of 128bit
0x6116_0300;
0x6116_0304; --> relevant data to Slave
0x6116_0308;
0x6116_030c;
second transfer of 128bit
0x6116_0310;
0x6116_0314;--> relevant data to Slave
0x6116_0318;
0x6116_031c;
third transfer of 128bit
0x6116_0320;
0x6116_0324;--> relevant data to Slave
0x6116_0328;
0x6116_032c;
This seems a bit odd... Who makes sure the data is ready in a correct manner for the Slave?
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6. case scenario READ:
arlen = 2 (3 read transfers)
arsize = 1 (16bit per each transfer)
arburst = 0 (FIXED)
araddr = 0x6116_0302;
7. In that case, the relevant 16bit read data from the 128bit would be --> 16 16 _ 16 16 _ 16 16 _ 16 16
Three read transfers which all act the same.
8. Second question:
Is that scenario correct?
Again, it seems odd to use the AXI this way. Who should arrange the read data in the memory?
Thank you in advanced.
P.S
I really would like to thank thoses who reply and enrich my AXI knowledge, I just don't know how to send a reply message.
Hello,
The AXI FIXED burst means that the address and byte lanes are not changing for each transfer in a burst.
A FIXED burst is suitable for accessing a slave like a FIFO.
> 5. first question:
This is a FIXED-3 x 32-bit write burst to address 0x6116_0304. All 3 transfers will write to address 0x6116_0304. The valid WDATA will all appear on [62:32] of the data bus. The WSTRB can be 0 or 1 for the used byte lanes (to allow sparse write) and must be 0 for the unused byte lanes.
> 8. Second question:
Similarly, this is a FIXED-3 x 16-bit read burst to address 0x6116_0302. All 3 transfers will read address 0x6116_0302. The valid RDATA will all appear on [31:16] of the data bus. The master must only take the RDATA from [31:16] and discard all other bits.
Regards,
Xingguang