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Hello,
we are using ARM core cortex-M0 in our chipset and we would like to enhance our FW code quality by having a view on the code coverage of our test suite.
What are the available tools, hw / SW? what could be the advantage to adopt a M0+ core instead of M0?
Is there also some solution available on HW simulation environment?
Thanks
Hi there,
First thing you can do is to run your code in a instruction set simulator.
Many development tools provide instruction set simulator which can record the program execution easily.
If you use standard microcontroller hardware, some debug environments support Program Counter (PC) sampling via debug connection, which can provide statistical code coverage once you have run the code over a long period of time. Some of the code coverage can be deduced from PC addresses that is known to be executed. For example, if there is no branch in a function A, and if the PC sampling record showing one of the address inside function A is executed, you can then assume all instructions in function A are executed. Another case is that if function A always called function B, and if we know function A is executed, then function B is executed (you might need to further analysis execution path inside function B).
Obviously it is not easy to check if all code covered with PC sampling. Remaining coverage holes can be check by inserting breakpoint. If the breakpoint is hit, it is covered.
If you are a chip designer using the Cortex-M0, you can also run the simulation in a Verilog simulator.
If you look at the file "cm0_tarmac.v", you can see that it capture instruction address from a internal signal called "iaex".
Using Cortex-M0+ potentially could be better but it depends on the tools. Although it cannot do streaming instruction trace as in Cortex-M3/M4 with ETM, the MTB can be setup by the tool to halt the processor once the buffer reach a water level. So by continuously halting the core, collect instruction trace, and resume, you could still built up a instruction trace. However, this is intrusive to the system's operations. And I am not sure if current tools can do that.
regards,
Joseph
Hi,
Thanks for your useful answer. Which tools are able to map output of PC traces with the code and then build a code coverage report file?
Kind regards,
Alexis
Hi Alexis,
Assume you captured the PC value in a file during Verilog simulation, is that correct?
If you are using DS-5 (or Keil MDK), you can generate a disassembled listing using
fromelf -c -d -e -s my_test.elf > my_test.lst
Being a geek, I would create a simple Perl script that go through each line of code, extract the PC value and see if it is covered in the text file containing PC values.
Qemu has support for Cortex-M3 already, the ARM GCC embedded comes with examples how to run the code in Qemu... There is also a work-in-progress port that provides support for M0 and M4 emulation: sushihangover/qemu · GitHub
I am usualy using LCOV for the codecoverage analysis. Do you know if there is a smart way to convert data in the right format?
Regards,
Sorry, I don't know if there is any tool that can do that.
joseph