Hi there,
Here is an AHB slave module which only supports word access (HSIZE[2:0] = 3'b010).
I plan to put it in a SoC, in which masters and interconnect could launch byte, half-word and word transcation.
Till now, I have 2 ideas to deal with that slave module:
Idea 1 --- Restrict software programming with only word operating instruction
Idea 2 --- Or, add some hardware logic
[write access]
* buffer byte or half-word from master
* halt the bus by deasserting READY signal
* Read remained triple bytes or half-word from slave to buffer
* Then write back the whole word in buffer to slave, and assert READY signal
[read access]
* Read the whole word from slave in word-align way
* Clear unneeded triple bytes or half-word in the whole word
* Send the whole word to master
I want to know if any other better idea for that ?
Any suggestion is appreciated.
As a matter of interest, why would you want to put in byte access if the designer of the slave module thought it was good enough to only provide word access? I'd just make certain the effects of a mismatch were defined even if only to do nothing though I prefer errors.
Hi Daith,
For example, my SoC has a Cortex-M3 processor, which can launch byte or half-word access. It depends on s/w and its compiler.
I think "Idea 1" would be simpler and more straight-forward.