Does AMBA 4 ACE backward compatible with AXI3?

AXI4 supports QoS signaling and removes some transfer types which you can find detail explanation from the technical reference manual of AXI4. 

AXI4 supports QoS signaling and removes some transfer types which you can find detail explanation from the technical reference manual of AXI4. 

AMBA 4 ACE is a superset of AMBA 4 AXI4, it adds the additional channels for coherency. ARM processors with AMBA 4 ACE support such as Cortex-A7, A15, A17, A53 and A57 can disable the ACE features and work in an AXI mode (generally AXI3 or AXI4).

There are 3 differences between AXI3 and AXI4:

* AXI4 adds longer burst support (not relevant to ARM CPUs)

* AXI4 adds the QOS signals (a 4 bit field often used as a priority indicator, again not driven by ARM CPUs)

* AXI4 removes the WID (write data ID field) as it expects write data to be in-order within a burst, and not interleaved

Most recent ARM system IP will be designed for AXI4 but will support some connection to legacy AXI3 peripherals. For example, the CoreLink CCI-400 Cache Coherent Interconnect includes the WID output on master interfaces to make it easier to connect to AXI3 peripherals, however it will not split the longer AXI4 bursts. The CoreLink NIC-400 network interconnect allows you to chose AXI3 or AXI4 interfaces and will insert the appropriate bridges if there is any conversion required.

Thanks,

Neil.