Usage of gathering and reordering in the ARMv8

Gathering

Let's say your code does 4 byte loads to consecutive addresses:

ldrb x0, =0x0000000000000000

ldrb x1, =0x0000000000000001

ldrb x2, =0x0000000000000002

ldrb x3, =0x0000000000000003

The processor could do 4 byte loads on the bus or it could get the same data by loading a word from address 0x0000000000000000.  If you describe the memory as non-gathering you will guaranteed to get the 4 byte accesses, if the memory allows gathering the access can be merged into a single word access (but it might not.)

Reordering

Let's say we have two stores:

str x0, [A]

str x1, [B]

Which memory address gets accessed first?

If we allow reordering we basically don't care, could be A then B or it could be B then A.  If we don't allow re-ordering then we must write to address A before address B.

Gathering and re-ordering allow the processor to optimise memory accesses so you want to allow them unless you have a reason not to.  This generally means peripheral space when those addresses are not RAM but MMIO registers in which case access order and size matter.  If 'A' is a DMA address register and 'B' is the control register that starts a transfer then we need the access to happen in order.

Gathering

Let's say your code does 4 byte loads to consecutive addresses:

ldrb x0, =0x0000000000000000

ldrb x1, =0x0000000000000001

ldrb x2, =0x0000000000000002

ldrb x3, =0x0000000000000003

The processor could do 4 byte loads on the bus or it could get the same data by loading a word from address 0x0000000000000000.  If you describe the memory as non-gathering you will guaranteed to get the 4 byte accesses, if the memory allows gathering the access can be merged into a single word access (but it might not.)

Reordering

Let's say we have two stores:

str x0, [A]

str x1, [B]

Which memory address gets accessed first?

If we allow reordering we basically don't care, could be A then B or it could be B then A.  If we don't allow re-ordering then we must write to address A before address B.

Gathering and re-ordering allow the processor to optimise memory accesses so you want to allow them unless you have a reason not to.  This generally means peripheral space when those addresses are not RAM but MMIO registers in which case access order and size matter.  If 'A' is a DMA address register and 'B' is the control register that starts a transfer then we need the access to happen in order.