• State Accepted Answer
  • Locked Locked
  • Replies 2 replies
  • Subscribers 349 subscribers
  • Views 5190 views
  • Users 0 members are here
Options
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Organization of startup from internal flash of Cortex M3

Volker Kugler

Hi,

i want to understand how the startup of a cortex M3 works. When i debug the startup i saw that from adress 0x0 a big area with DCW comes, like here:

0x00000000 0268  DCW  0x0268
0x00000002 2000  DCW  0x2000
0x00000004 0505  DCW  0x0505
0x00000006 0000  DCW  0x0000
0x00000008 050D  DCW  0x050D
0x0000000A 0000  DCW  0x0000
0x0000000C 050F  DCW  0x050F
0x0000000E 0000  DCW  0x0000
0x00000010 0511  DCW  0x0511
0x00000012 0000  DCW  0x0000
0x00000014 0513  DCW  0x0513

Later followed from that:

0x000001CA 0000  DCW  0x0000
0x000001CC 051F  DCW  0x051F
0x000001CE 0000  DCW  0x0000
             __main:
0x000001D0 F000F802  BL.W __scatterload (0x000001D8)
0x000001D4 F000F83A  BL.W __rt_entry (0x0000024C)
             __scatterload:
0x000001D8 A00A  ADR  r0,{pc}+4  ; @0x00000204
0x000001DA E8900C00  LDM  r0,{r10-r11}
0x000001DE 4482  ADD  r10,r10,r0
0x000001E0 4483  ADD  r11,r11,r0
0x000001E2 F1AA0701  SUB  r7,r10,#0x01
             __scatterload_null:

but if i debug i saw that this section was first excuted:

0x00000500 0334  DCW  0x0334
0x00000502 0640  DCW  0x0640
   195:             LDR R0, =SystemInit
0x00000504 4809  LDR  r0,[pc,#36]  ; @0x0000052C
   196:             BLX R0
0x00000506 4780  BLX  r0
   197:             LDR R0, =__main
0x00000508 4809  LDR  r0,[pc,#36]  ; @0x00000530
   198:             BX  R0

Can anybody explain me how the startup exactly works and what is the meaning of the DCW part?

So which assembler directive calls the SystemInit?

Best regards

Volker

0