Does Cortex-A12 not supprt AMBA4 ACE protocol?
The figure and description of the Cortex-A12 product page(http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php) shows as if it only supports "AMBA4 AXI Bus" is available bus interface.
(1) Is that not correct?
It's not correct - Cortex-A17 provides the cache coherent equivalent of Cortex-A12 (and significantly higher performance). The latest version of this data can be found on the products page:
http://www.arm.com/products/processors/cortex-a/cortex-a12-processor.php
... which lists the main port as AXI4 only.
(2) Did the core has any problem that could not be fixed if users would like to use AMBA ACE protocol to implement cache coherent operation?
It doesn't support it, so you can't support cache coherent operation.
(3) If the core doesn't support ACE protocol, is it meaningless to use cache coherent controller(ex, CCI400) for cache coherent feature?
Unless you have other masters in the system which need it, yes, you won't get any added benefit from a cache coherent bus vs a non-coherent bus.
HTH, Pete
Thanks, Pete, for clarifying.
The original TechCon presentation was one of mine. I have looked at the source slides and the mistake comes down to an error in an earlier version of the marketing diagram for the Cortex-A12. As you can see, this has been corrected in the version currently displayed on Cortex-A12 page on our website.
I apologise for the error in the presentation and hope that it hasn't caused too much confusion.
Glad it's cleared up now!
Regards
Chris
So, CA12 not support ACE means:
CA12 could not be used with CA7 in a big.LITTLE design?
Correct - the big.LITTLE equivalent of this would be a pairing of Cortex-A17 with Cortex-A7.