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Hi,
I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
Thanks
Hi Vivek,
Good to know that you are already working with the university program. I will contract them to see if there is anything they can do to help.
My books are focus on MCU users, so it doesn't cover Cortex-M hardware (e.g. AHB anf FPGA) design topics.
Regarding sampling analog inputs, there are several options you should consider:
- if the two analogue inputs are stero audio inputs (L+R channels), maybe you should use I2S protocol instead. It is much easier than I2C. (Just some serial to parallel shift registers and a simple FSM).
- You can use ADC with parellel interface (there is a AHB GPIO module in the EDK).
- You can use GPIO to create bit banging operations to emulate I2C operations, which will then allow you to connect the system to a I2C module. But this means you need to have good understanding of the I2C protocol to do that.
regards,
Joseph