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Design Start ARM Cortex-M0

vivek

Hi,

I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.

I searched on  internet which shows interfacing only through core generator (MIG). Is there a way I can use  Xilinx core generator to interface through AHB lite system.

I am using  Atlys Xilinx Spartan 6.

I also have some  example SoC design which interface 128Mb SRAM  to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using  has DDR2 RAM.

Thanks

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  • 0 Arm Employee Badge in reply to vivek

    Without seeing what you have got in your simulation it is hard to guess what went wrong.

    Please note ARM_SOC1 instantiate AHB2MEM_V2.v  (see the pdf of the slide in the project directory).

    Please make sure you are selecting the right file in your project.

    (This load code.hex from software directory.)

    regards,

    Joseph

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  • 0 Arm Employee Badge in reply to vivek

    Without seeing what you have got in your simulation it is hard to guess what went wrong.

    Please note ARM_SOC1 instantiate AHB2MEM_V2.v  (see the pdf of the slide in the project directory).

    Please make sure you are selecting the right file in your project.

    (This load code.hex from software directory.)

    regards,

    Joseph

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