hi, experts:
I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.
I have some questions about out cache concept in Cortex-A7.1. Some program disable outer cache by setting ACTLR[1] = 0.
So, is it only available with Cortex-A9?
In Cortex-A7 MPCore manual: ACTLR[1] is reserved, so could not disablt outer cache by this method, right?
2. Outer cache question
In Cortex-A7, L2 Cache controller is also integrated into SCU, so have not outer cache concept, right?
3. In Cortex-A7, SCTLR[2] used to control DCache enable or not.
So, if wanting to disable DCache, just set SCTLR[2] = 0, not need to disable outer cache(such as L2 Cache) anymore, right?
4. In Cortex-A7, user could not only turn on L1 DCache, and disable L2 Cache, right?
User must turn L1 DCache and L2 Cache at the same time.
And if user set SCTLR[2] = 0, then he has disabled L1 DCache and L2 Cache at the same time, right?
best wishes,
Hi,
for Q1, ACTLR[1] in Cortex-A9 represents L2 prefetch enable. And the feature must be enabled only when the slaves connected on the Cortex-A9 AXI master port support it. So I wouldn't say "it disables outer cache" The encodings of ACTLR are different among processors. So any control mechanism based on ACTLR wouldn't be very generic.
for Q2, outer and inner are relative concepts, it depends on your reference point. L2 cache could be inner if there was L3, and it could be outer relative to L1. And integrated L2 in A7 is optional, so I wouldn't say A7 doesn't have outer cache concept.
for Q3 and Q4, again, tightly integrated L2 cache is optional as well as L2 cache controller. The bits in SCTLR only matters for L1. For L2, it should be L2 cache controller's responsibilities, such as PL310
Best regards,
George