I am using Cortex m4 processor from freescale K22,
In boot loader i download my firmware and after that I do following steps to soft restart
// Disable - WatchDog and disbled IRQ.
WDT_DISABLE();
Disable_ALL_IRQ();
DisableInterrupts;
// Small delay is required before Soft RESET.
delay1S();
// SOFT RESET For K20
SCB_AIRCR = SCB_AIRCR_VECTKEY(0x05FA) | SCB_AIRCR_SYSRESETREQ(1) ;
Now when MCU gets soft restart signal, next time it goes into CORE LOCK UP state
Ref:
ARM Information Center
Also after soft restart, i take jump to firmware with ODD address so as to ensure it is thumb mode.
my firmware address is 0X5000 + 1
Then it remains in Hard fault mode until i give power on reset then this hard fault state never occurs.
Can any body tell why this Hard fault state occurs when I soft restart??????
Thanks in advance!!!
The connections from the reset request signal (generated by the processor) to the actual reset controller on the chip are designed by Freescale, so we don't have the details and couldn't give you any additional help.
Potentially the Freescale chip might have additional reset control registers in the watchdog or system management blocks that you can use for resetting the system.
A few other suggestions:
- if you are buying the chips from a distributor, you might be able to get support from your distributor.
- there are some resources on debugging fault exceptions on the web:
Keil MDK application note: 209:Using Cortex-M3 and Cortex-M4 Fault Exceptions
Presentation from niallcooling (Feabhas
http://www.hitex.co.uk/fileadmin/uk-files/pdf/ARM%20Seminar%20Presentations%202013/Feabhas%20Developing%20a%20Generic%20…
https://community.freescale.com/thread/306244
I am sure you can find additional resources on this topic easily.
regards,
Joseph
(I am the author of the books, but not famous )
Following on from Joseph's kind reference, I've also posted about the hard fault handler which might be easier to understand at:
http://blog.feabhas.com/2013/02/setting-up-the-cortex-m34-armv7-m-memory-protection-unit-mpu/