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How does ARM11 respond to a non-secure interrupt in secure mode?

Dong Luo
Note: This was originally posted on 19th March 2009 at http://forums.arm.com

Hi All,
Assuming that ARM11 is running a secure process and receives a non-secure IRQ or FIQ, how does ARM11 respond to a non-secure interrupt? What should hardware do? And, what should software do? How does ARM11 guarantee that data of secure world not expose to the non-secure interrupt? Can anybody clarify the above questions? Thanks.
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  • +1 Arm Employee Badge
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    It depends on the configuration of the Secure Configuration Register set by the Secure World code, and the status of the I and F interrupt masks in the CPSR when running in the Secure World.

    > How does ARM11 guarantee that data of secure world not expose to the non-secure interrupt?

    The hardware enforces banking of critical CP14/15 registers - but the software is responsible for security of the general purpose registers (and VFP, etc). The hardware will just route the interrupt to monitor mode if that is how the SCR is configured - monitor mode software must ensure that no secure data in registers leaks across to the normal world.
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  • +1 Arm Employee Badge
    Note: This was originally posted on 19th March 2009 at http://forums.arm.com

    It depends on the configuration of the Secure Configuration Register set by the Secure World code, and the status of the I and F interrupt masks in the CPSR when running in the Secure World.

    > How does ARM11 guarantee that data of secure world not expose to the non-secure interrupt?

    The hardware enforces banking of critical CP14/15 registers - but the software is responsible for security of the general purpose registers (and VFP, etc). The hardware will just route the interrupt to monitor mode if that is how the SCR is configured - monitor mode software must ensure that no secure data in registers leaks across to the normal world.
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