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ARM1176JZ-S, cache confg: effective cache size calculation

deven deven
Note: This was originally posted on 22nd February 2009 at http://forums.arm.com

Hello,

1) I am using ARM1176JZ-S core with WinCE Platform. The cache memory is configured as follows

    DCache: 128 sets, 4 ways, 32 line size, 16384 size
    ICache: 128 sets, 4 ways, 32 line size, 16384 size

    Now I want to know the effective data cache size, I mean the total data from the main memory 
    could be cached and accessed without cache trashing within a function.

2) Is the cache set size(128 sets) and cache block/segment(of other processors) size are same?

Kindly reply this mail, thanks in advance

Regards,
Deven
Parents
  • 0
    Note: This was originally posted on 25th February 2009 at http://forums.arm.com

    Hello isogen74,

    Thanks for the information.

    From your explanation, does it mean there is only one segment and the effective cache size is 4KB.

    Main memory          ...........................  data cache memory
    ===========...........................  ==============
        0-1023 bytes              ---------------------->    0- 4095 bytes               (4way)
    ===========...........................  ==============
    1024-2047 bytes            ---------------> 4096- 8191 bytes            (4way)
    ===========-...........................  -==============
    2048-3071 bytes           --------------->  8192- 12887 bytes          (4way)
    ===========...........................  ==============
    3072- 4096bytes           --------------->  12888-16384 bytes          (4way)
    ===========...........................  ==============
    effective size = 4KB



    Pls clarify.

    thanks,
    Deven





    > I mean the total data from the main memory 

    16KB for data, and 16KB for instructions are the critical numbers you will want. The rest is just noise unless you design a pathological algorithm which really abuses the cache.

    Some systems also include a L2 cache which can cache more data between the L1 caches and the main memory.

    > Is the cache set size(128 sets) and cache block/segment(of other processors) size are same?

    It varies - basically the scheme you outline means that for any 1 address there are 4 possible places (ways) where the data may reside. 128 sets (cache lines) * 4 ways * 32-bytes per cache line = 16 KB. Four 4-way caches are pretty common as they give a good trade-off between  speed and cache utilization for typical code.

    For most caches on ARM systems the number of ways is fixed, but number of sets depends on the size of the cache. In this case 64 sets = 8KB cache, 128 sets = 16KB cache, etc.
Reply
  • 0
    Note: This was originally posted on 25th February 2009 at http://forums.arm.com

    Hello isogen74,

    Thanks for the information.

    From your explanation, does it mean there is only one segment and the effective cache size is 4KB.

    Main memory          ...........................  data cache memory
    ===========...........................  ==============
        0-1023 bytes              ---------------------->    0- 4095 bytes               (4way)
    ===========...........................  ==============
    1024-2047 bytes            ---------------> 4096- 8191 bytes            (4way)
    ===========-...........................  -==============
    2048-3071 bytes           --------------->  8192- 12887 bytes          (4way)
    ===========...........................  ==============
    3072- 4096bytes           --------------->  12888-16384 bytes          (4way)
    ===========...........................  ==============
    effective size = 4KB



    Pls clarify.

    thanks,
    Deven





    > I mean the total data from the main memory 

    16KB for data, and 16KB for instructions are the critical numbers you will want. The rest is just noise unless you design a pathological algorithm which really abuses the cache.

    Some systems also include a L2 cache which can cache more data between the L1 caches and the main memory.

    > Is the cache set size(128 sets) and cache block/segment(of other processors) size are same?

    It varies - basically the scheme you outline means that for any 1 address there are 4 possible places (ways) where the data may reside. 128 sets (cache lines) * 4 ways * 32-bytes per cache line = 16 KB. Four 4-way caches are pretty common as they give a good trade-off between  speed and cache utilization for typical code.

    For most caches on ARM systems the number of ways is fixed, but number of sets depends on the size of the cache. In this case 64 sets = 8KB cache, 128 sets = 16KB cache, etc.
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