• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 9 replies
  • Subscribers 349 subscribers
  • Views 9099 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ARM9 replacing Cortex M3

Michael von Hauff
Parents
  • 0
    Note: This was originally posted on 8th January 2009 at http://forums.arm.com

    Hi Mike,

    The issue you are facing is not a limitation of the CPU core, but a limitation of the system level design.  Even with a 200MHz or 400MHz ARM9, it might not be able to reach your targeted DMA speed because the DMA bandwidth is limited by a number of factors outside the CPU core:
    - DMA controller design (microcontroller vendor specific)
    - bus frequency (cpu clock, system bus and peripheral bus can all have different operation frequency. E.g. the Atmel's AT91SAM9G20 can reach 400MHz for the CPU core, but system bus is 133MHz)
    - Peripheral bus bridge latency (If GPIO is on APB periheral bus, each transfer takes at least 2 cycles, and bus bridge itself might add additional latency)
    - SRAM access speed (usually it is zero waitstate for internal SRAM)
    - Bus access priority (if both CPU and DMA try to access SRAM/GPIO at the same time, which one has higher priority?)

    I am not saying it cannot be done. I just want to point out the areas you need to check. Hope this can help your device selection.

    On a completely different approch, have you consider using FPGA with Cortex-M1?
    Joseph
Reply
  • 0
    Note: This was originally posted on 8th January 2009 at http://forums.arm.com

    Hi Mike,

    The issue you are facing is not a limitation of the CPU core, but a limitation of the system level design.  Even with a 200MHz or 400MHz ARM9, it might not be able to reach your targeted DMA speed because the DMA bandwidth is limited by a number of factors outside the CPU core:
    - DMA controller design (microcontroller vendor specific)
    - bus frequency (cpu clock, system bus and peripheral bus can all have different operation frequency. E.g. the Atmel's AT91SAM9G20 can reach 400MHz for the CPU core, but system bus is 133MHz)
    - Peripheral bus bridge latency (If GPIO is on APB periheral bus, each transfer takes at least 2 cycles, and bus bridge itself might add additional latency)
    - SRAM access speed (usually it is zero waitstate for internal SRAM)
    - Bus access priority (if both CPU and DMA try to access SRAM/GPIO at the same time, which one has higher priority?)

    I am not saying it cannot be done. I just want to point out the areas you need to check. Hope this can help your device selection.

    On a completely different approch, have you consider using FPGA with Cortex-M1?
    Joseph
Children
No data