Arm Community
Site
Search
User
Site
Search
User
Support forums
Architectures and Processors forum
hard fault with Cortex M1
Jump...
Cancel
State
Not Answered
Locked
Locked
Replies
10 replies
Subscribers
348 subscribers
Views
11817 views
Users
0 members are here
Cortex-M1
Cortex-M
firmware
Options
Share
More actions
Cancel
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion
hard fault with Cortex M1
sumit sumit
over 12 years ago
Note: This was originally posted on 24th December 2008 at
http://forums.arm.com
Hi all,
I am developing firmware on Cortex M1 on Actel fusion FPGA.I have built the design that has sram at 0x0 location ,size is 1mb and I use it as my program memory.I have Ethernet interface and I want to debug the driver for the ipcore.
I am facing the problem due to hard fault.When I start the transmission on the Ethernet,after transmission first frame the cortex goes to hard fault.
Would anyone tell me what may be the reason for hard fault? How to overcome?
I am completely new to arm environment.
regards,
Sumit
Parents
0
Tobias Hondorf
over 12 years ago
Note: This was originally posted on 8th December 2009 at
http://forums.arm.com
I get a hardfault expection aswell. I checked my pointers, everything seems to be OK. I'm currently porting an microKernel to the M1, so i adjust StackPointer to different Stacks in Memory (Task Control Blocks) i checked my code, i don't think i make a misstake there. But it seems the the crash occures after the ContextSwitch. And it only occures in running mode, when i step i never leave the IRQ handler, but this might be because interrupts coming fast enough to inflict a new IRQ before i stepped through one.
Well i sticked a breakpoint to the begin of the HardFault handler, and checked the memory adress of the StackPointer+24. This should be the ReturnAddress that has been saved automaticly on the stack while entering the (fault) exception. But for some reason i got only the initial value (a5a5a5a5) of this memory section at the address. There seems to be nothing written. I got a value in the saved LR (SP+20) and a value in the saved xPSX (SP+28) memory, which seems to be both correct.
How can this happen? Since the procedure which pushes the 8 registers on entry of exception on the stack is pushing xPSR than returnAdress and than LR. So i't cant be an issue with abort of this push function - if there were the LR have to be empty aswell.
I just wonder how to track this error. I have no idea how to debug this.
I afforded 2 days in verifying my code with teammates, cant find an error there. Neither in the C Source nor in the Assembly which contains the context switch.
I already wrote a port for another kernel, worked and was easy going.
From all what i can find in the Reference Manuals, the Internet and this Forum it seems to be an issue with the Stackpointer, but in stepping mode its working as expected. And i reviewed my program architecture - dont think the error is coming from there.
What ever, I'd really appreciate it if someone got an idea how to backtrack this hardfault. Thanks in advance.
Cancel
Vote up
0
Vote down
Cancel
Reply
0
Tobias Hondorf
over 12 years ago
Note: This was originally posted on 8th December 2009 at
http://forums.arm.com
I get a hardfault expection aswell. I checked my pointers, everything seems to be OK. I'm currently porting an microKernel to the M1, so i adjust StackPointer to different Stacks in Memory (Task Control Blocks) i checked my code, i don't think i make a misstake there. But it seems the the crash occures after the ContextSwitch. And it only occures in running mode, when i step i never leave the IRQ handler, but this might be because interrupts coming fast enough to inflict a new IRQ before i stepped through one.
Well i sticked a breakpoint to the begin of the HardFault handler, and checked the memory adress of the StackPointer+24. This should be the ReturnAddress that has been saved automaticly on the stack while entering the (fault) exception. But for some reason i got only the initial value (a5a5a5a5) of this memory section at the address. There seems to be nothing written. I got a value in the saved LR (SP+20) and a value in the saved xPSX (SP+28) memory, which seems to be both correct.
How can this happen? Since the procedure which pushes the 8 registers on entry of exception on the stack is pushing xPSR than returnAdress and than LR. So i't cant be an issue with abort of this push function - if there were the LR have to be empty aswell.
I just wonder how to track this error. I have no idea how to debug this.
I afforded 2 days in verifying my code with teammates, cant find an error there. Neither in the C Source nor in the Assembly which contains the context switch.
I already wrote a port for another kernel, worked and was easy going.
From all what i can find in the Reference Manuals, the Internet and this Forum it seems to be an issue with the Stackpointer, but in stepping mode its working as expected. And i reviewed my program architecture - dont think the error is coming from there.
What ever, I'd really appreciate it if someone got an idea how to backtrack this hardfault. Thanks in advance.
Cancel
Vote up
0
Vote down
Cancel
Children
No data