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hard fault with Cortex M1

sumit sumit
Note: This was originally posted on 24th December 2008 at http://forums.arm.com

Hi all,

I am developing firmware on Cortex M1 on Actel fusion FPGA.I have built the design that has sram at 0x0 location ,size is 1mb and I use it as my program memory.I have Ethernet interface and I want to debug the driver for the ipcore.

I am facing the problem due to hard fault.When I start the transmission on the Ethernet,after transmission first frame the cortex goes to hard fault.

Would anyone tell me  what may be the reason for hard fault? How to overcome?

I am completely new to arm environment.

regards,
Sumit
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  • 0
    Note: This was originally posted on 8th December 2009 at http://forums.arm.com

    Not sure if it help, there are various things you might need to check.
    First, please check if the FPGA image you are using contains the OS support.
    (On Cortex-M1 OS support hardware is optional).

    What might have happen is that :
    - you created your stack frame in the stack
      (Is the content of the stack frame correct?
      If the stack frame aligned to double word address?)
    - you set your process stack pointer (PSP) to point to the beginning of this stack frame
      (Did you update PSP correctly?
      Did you take account of the requirement of double word alignment?
      Does the PSP really pointing to the correct address in the stack frame?)
    - You carry out an exception return, LR specifying using PSP for unstacking.
      (did LR set to correct value?)
    - The exception return load the stack frame contents into registers.
      If the PSP location is wrong, the processor loaded in incorrect values.
      This include the 0xa5a5a5a5 loading into PC. Since this is not a valid location
      for program code, the hard fault is triggered when it try to fetch instruction.
    - At hard fault exception entry, the value 0xa5a5a5a5 is pushed to the stack as return address.
    regards,
    Joseph
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  • 0
    Note: This was originally posted on 8th December 2009 at http://forums.arm.com

    Not sure if it help, there are various things you might need to check.
    First, please check if the FPGA image you are using contains the OS support.
    (On Cortex-M1 OS support hardware is optional).

    What might have happen is that :
    - you created your stack frame in the stack
      (Is the content of the stack frame correct?
      If the stack frame aligned to double word address?)
    - you set your process stack pointer (PSP) to point to the beginning of this stack frame
      (Did you update PSP correctly?
      Did you take account of the requirement of double word alignment?
      Does the PSP really pointing to the correct address in the stack frame?)
    - You carry out an exception return, LR specifying using PSP for unstacking.
      (did LR set to correct value?)
    - The exception return load the stack frame contents into registers.
      If the PSP location is wrong, the processor loaded in incorrect values.
      This include the 0xa5a5a5a5 loading into PC. Since this is not a valid location
      for program code, the hard fault is triggered when it try to fetch instruction.
    - At hard fault exception entry, the value 0xa5a5a5a5 is pushed to the stack as return address.
    regards,
    Joseph
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