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Testing for interrupt

Upp3r Upp3r
Note: This was originally posted on 19th November 2008 at http://forums.arm.com

Im looking for a way to test if there is an interrupt currently processing on my ARM7. I can see that the interrupt disable bits are set to disable the FIQ and IRQ interrupts, but are they set when an interrupt is triggered? In my "TMS470R1x User's Guide" in the section on Exceptions, it gives a run down when an exception occurs and it says it "may also set interrupt disable flags" but nothing decisive.
My question is:  Do the CPSR I and F bits  signify there is an interrupt in progress, i.e, when an interrupt occurs, is the disable flag set? If not, how could I determine if there is an interrupt in progress?
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