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ARM Cortex-A9 | Non-cacheable memory range

S R Chidrupaya
Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

Hi all,


I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application which retrieves and stores data on DDR3(on zynq), that in turn is stored or retrieved by another part of the application running on microblaze(zynq).

For maintaining coherency between them I need to make the data accesses non-cacheable. Is there any provision on arm to make a range of memory non-cacheable during run-time?

Thanks

John
Parents
  • 0 Arm Employee Badge
    Note: This was originally posted on 3rd June 2013 at http://forums.arm.com


    Thank you for clearing it up for me. [...]  So from what I understand I have to change the memory attributes in the MMU table, but as I have informed there is a problem in that. I was hoping to achieve the remapping by changing the "cp15 c10" registers,


    Well, my description is a bit oversimplified.  It is possible to use "TEX remap" (SCTRL.TRE == 1) which means that the memory attributes are determined by using three bits in the translation table entries as an index into a table held the c10 registers (PRRR and NMRR).  So it is possible to set things up so that you can switch the Shareability by changing just the PRRR and/or NMRR registers (and doing the necessary TLB flushing).
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  • 0 Arm Employee Badge
    Note: This was originally posted on 3rd June 2013 at http://forums.arm.com


    Thank you for clearing it up for me. [...]  So from what I understand I have to change the memory attributes in the MMU table, but as I have informed there is a problem in that. I was hoping to achieve the remapping by changing the "cp15 c10" registers,


    Well, my description is a bit oversimplified.  It is possible to use "TEX remap" (SCTRL.TRE == 1) which means that the memory attributes are determined by using three bits in the translation table entries as an index into a table held the c10 registers (PRRR and NMRR).  So it is possible to set things up so that you can switch the Shareability by changing just the PRRR and/or NMRR registers (and doing the necessary TLB flushing).
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