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ARM Cortex-A9 | Non-cacheable memory range

S R Chidrupaya
Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

Hi all,


I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application which retrieves and stores data on DDR3(on zynq), that in turn is stored or retrieved by another part of the application running on microblaze(zynq).

For maintaining coherency between them I need to make the data accesses non-cacheable. Is there any provision on arm to make a range of memory non-cacheable during run-time?

Thanks

John
Parents
  • 0 Arm Employee Badge
    Note: This was originally posted on 24th May 2013 at http://forums.arm.com

    The cacheability of a memory region is determined by the MMU tables.  If you're maintaining the MMU tables yourself then to switch from cacheable to non-cacheable you'd need to clean any dirty data for the region from the cache(s) and then change the MMU tale to make it non-cacheable.  The reverse is similar but there's no need to clean any cache.

    If you're using an OS then you'll have to get it to do the cache maintenance and MMU table updates.

    [size=2]Alternatively, if you can make use of the ACP on the Cortex-A9/SCU you can let it take care of cache coherency with another master.  How to do this on Zynq is something you'll need to ask Xilinx about.[/size]
Reply
  • 0 Arm Employee Badge
    Note: This was originally posted on 24th May 2013 at http://forums.arm.com

    The cacheability of a memory region is determined by the MMU tables.  If you're maintaining the MMU tables yourself then to switch from cacheable to non-cacheable you'd need to clean any dirty data for the region from the cache(s) and then change the MMU tale to make it non-cacheable.  The reverse is similar but there's no need to clean any cache.

    If you're using an OS then you'll have to get it to do the cache maintenance and MMU table updates.

    [size=2]Alternatively, if you can make use of the ACP on the Cortex-A9/SCU you can let it take care of cache coherency with another master.  How to do this on Zynq is something you'll need to ask Xilinx about.[/size]
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