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ARM Cortex-A9 | Non-cacheable memory range

S R Chidrupaya
Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

Hi all,


I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application which retrieves and stores data on DDR3(on zynq), that in turn is stored or retrieved by another part of the application running on microblaze(zynq).

For maintaining coherency between them I need to make the data accesses non-cacheable. Is there any provision on arm to make a range of memory non-cacheable during run-time?

Thanks

John
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  • 0
    Note: This was originally posted on 3rd June 2013 at http://forums.arm.com

    Hi Scott and isogen,

    Thanks for clearing it up, Scott. But if I do use the table entries(or MMU) to remap the memory regions, as per my understanding, I've to do it for a section with size range(4kB - 1MB) which I want to avoid as my need is to declare only a range of memory as non-cacheable. If I'm missing anything; please suggest.

    John
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  • 0
    Note: This was originally posted on 3rd June 2013 at http://forums.arm.com

    Hi Scott and isogen,

    Thanks for clearing it up, Scott. But if I do use the table entries(or MMU) to remap the memory regions, as per my understanding, I've to do it for a section with size range(4kB - 1MB) which I want to avoid as my need is to declare only a range of memory as non-cacheable. If I'm missing anything; please suggest.

    John
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