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ARM Cortex-A9 | Non-cacheable memory range

S R Chidrupaya
Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

Hi all,


I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application which retrieves and stores data on DDR3(on zynq), that in turn is stored or retrieved by another part of the application running on microblaze(zynq).

For maintaining coherency between them I need to make the data accesses non-cacheable. Is there any provision on arm to make a range of memory non-cacheable during run-time?

Thanks

John
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  • 0
    Note: This was originally posted on 31st May 2013 at http://forums.arm.com

    Hi Scott,

    Thank you for clearing it up for me. I mean to change the memory attributes of the physical addresses themselves, but perhaps changing the bit field of the TTBRx registers would only change the way the TLB walks are peformed(on cacheable memory or not) , not really what I need. So from what I understand I have to change the memory attributes in the MMU table, but as I have informed there is a problem in that. I was hoping to achieve the remapping by changing the "cp15 c10" registers, but modifying the TLB entries or translation tables(thanks!) would result in the same problem. I do not find any other option for implementing this feature.
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  • 0
    Note: This was originally posted on 31st May 2013 at http://forums.arm.com

    Hi Scott,

    Thank you for clearing it up for me. I mean to change the memory attributes of the physical addresses themselves, but perhaps changing the bit field of the TTBRx registers would only change the way the TLB walks are peformed(on cacheable memory or not) , not really what I need. So from what I understand I have to change the memory attributes in the MMU table, but as I have informed there is a problem in that. I was hoping to achieve the remapping by changing the "cp15 c10" registers, but modifying the TLB entries or translation tables(thanks!) would result in the same problem. I do not find any other option for implementing this feature.
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