• State Not Answered
  • Locked Locked
  • Replies 9 replies
  • Subscribers 348 subscribers
  • Views 15792 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ARM Cortex-A9 | Non-cacheable memory range

S R Chidrupaya
Note: This was originally posted on 23rd May 2013 at http://forums.arm.com

Hi all,


I am designing an application on  xilinx zynq 702 board which comes with two(core) arm cortex a9 processors. I am using one of the arm cores two run a part of the application which retrieves and stores data on DDR3(on zynq), that in turn is stored or retrieved by another part of the application running on microblaze(zynq).

For maintaining coherency between them I need to make the data accesses non-cacheable. Is there any provision on arm to make a range of memory non-cacheable during run-time?

Thanks

John
Parents
  • 0
    Note: This was originally posted on 28th May 2013 at http://forums.arm.com

    Hello Scott,


    Thank you for your suggestion. In my current design I'm using AXI-HP, so maintaining coherency falls on the part of application(baremetal). I understand that by following the procedures mentioned by you I can declare a section(1 MB or 4KB) of memory in the TLB as cacheable or non-cacheable. But the need is to declare a range of memory as non-cacheable. One way of doing this could be declaring a range of memory(at runtime) as non-cacheable(TTBR register) while performing TLB walks, when its included in the TLB. But I'm unable to get any further reference to this method.

    Can you please give any suggestion as to if the above mentioned path is feasible or do I need to follow any other possible way.


    Thanks

    John
Reply
  • 0
    Note: This was originally posted on 28th May 2013 at http://forums.arm.com

    Hello Scott,


    Thank you for your suggestion. In my current design I'm using AXI-HP, so maintaining coherency falls on the part of application(baremetal). I understand that by following the procedures mentioned by you I can declare a section(1 MB or 4KB) of memory in the TLB as cacheable or non-cacheable. But the need is to declare a range of memory as non-cacheable. One way of doing this could be declaring a range of memory(at runtime) as non-cacheable(TTBR register) while performing TLB walks, when its included in the TLB. But I'm unable to get any further reference to this method.

    Can you please give any suggestion as to if the above mentioned path is feasible or do I need to follow any other possible way.


    Thanks

    John
Children
No data