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Cortex A8 Instruction Cycle Timing

Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(

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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 10th August 2011 at http://forums.arm.com

Well Anil.
I've tried some time to ask infomation to ARM.
They are very cool, but finaly they never answered me.

The problem you found is very specific, and the documentation is clear:

This chapter provides the information to estimate how much execution time particular code sequences require. The complexity of the processor makes it impossible to guarantee precise timing information with hand calculations.

I think that nobody knows every special case of NEON working (except maybe the guy who design it).
You can try

Exo,
I thaught NEON queue was 16 entries deep, and memory access queue was 8 or 12 entries deep !

I will try your load example, but for me, you can only pair un multi cycle instruction on it's first cycle OR it's last cycle.
the doc say's

There are also similar restrictions to the ARM integer pipeline in terms of dual issue pairing with multi-cycle instructions. The NEON engine can potentially dual issue on both the first and last cycle of a multi-cycle instruction, but not on any of the intermediate cycles.

Reading that, it seem's that your are right, but I think I had made tests about that, and I do not remember to have succefully pair one instruction twice.
I'll check again !
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0 Etienne SOBOLE over 12 years ago

Note: This was originally posted on 10th August 2011 at http://forums.arm.com

Well Anil.
I've tried some time to ask infomation to ARM.
They are very cool, but finaly they never answered me.

The problem you found is very specific, and the documentation is clear:

This chapter provides the information to estimate how much execution time particular code sequences require. The complexity of the processor makes it impossible to guarantee precise timing information with hand calculations.

I think that nobody knows every special case of NEON working (except maybe the guy who design it).
You can try

Exo,
I thaught NEON queue was 16 entries deep, and memory access queue was 8 or 12 entries deep !

I will try your load example, but for me, you can only pair un multi cycle instruction on it's first cycle OR it's last cycle.
the doc say's

There are also similar restrictions to the ARM integer pipeline in terms of dual issue pairing with multi-cycle instructions. The NEON engine can potentially dual issue on both the first and last cycle of a multi-cycle instruction, but not on any of the intermediate cycles.

Reading that, it seem's that your are right, but I think I had made tests about that, and I do not remember to have succefully pair one instruction twice.
I'll check again !
Cancel
Vote up 0 Vote down

Cancel

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