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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 15th August 2011 at http://forums.arm.com


    If I use three buffers with 4096 bytes size, the cycle count increases to around 140 cycles. I have given the code  here, r1,r2,r3 has the address of buffer1,buffer2 and buffer3 respectively.


    However, if the buffer size is not a multiple of 4096, cycle count is normal.


    140 cycles for each iteration of the loop ?
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  • 0
    Note: This was originally posted on 15th August 2011 at http://forums.arm.com


    If I use three buffers with 4096 bytes size, the cycle count increases to around 140 cycles. I have given the code  here, r1,r2,r3 has the address of buffer1,buffer2 and buffer3 respectively.


    However, if the buffer size is not a multiple of 4096, cycle count is normal.


    140 cycles for each iteration of the loop ?
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